History of XAP processor in Timeline

The XAP processor, developed by Cambridge Consultants, is a RISC architecture designed for low-power applications. Available in 16-bit and 32-bit versions, it targets mixed-signal integrated circuits commonly found in sensors and wireless technologies like Bluetooth, Zigbee, GPS, RFID, and NFC. Its key strength lies in its suitability for battery-powered, high-volume products where energy efficiency is paramount, which makes it ideal for wireless sensor networks and medical devices.

1994: XAP1 Design

In 1994, the XAP1 was designed for wireless and sensor ASIC projects at Cambridge Consultants. It was a very small, 3,000-gate, Harvard architecture, 16-bit processor intended for programs stored in on-chip ROM.

1999: XAP2 Microprocessor Launch

In 1999, the XAP2 microprocessor was developed and launched, incorporating a Harvard architecture and utilizing 16-bit data paths. It also adopted a more conventional 16-bit instruction width, enhancing its compatibility with program storage solutions, and was used in Cambridge Consultants' ASIC designs.

2003: XAP3 Experimental Processor Design

In 2003, the XAP3, an experimental 32-bit processor, was designed at Cambridge Consultants. It was optimized for low cost, low energy ASIC implementations and was the first of Cambridge Consultants’ processors to use a Von Neumann architecture.

2005: XAP4 Processor Design

In 2005, the XAP4, a new 16-bit processor, was designed to supersede the XAP2, taking into account the experience gained on XAP3 and the evolving requirements of ASIC designs. XAP4 is a very small, 12,000-gate, Von Neumann bus, 16-bit processor core capable of addressing a total of 64 Kbytes of memory.

2006: XAP5 Architecture Development

In 2006, development of an extended version of the XAP architecture commenced, resulting in the XAP5.

July 2008: XAP5 Announcement

In July 2008, the XAP5, a 16-bit processor with a 24-bit address bus, was announced. It is tailored to the requirements of small, low-energy ASICs.

2013: XAP6 Processor Launch

In 2013, the XAP6, a 32-bit processor, was launched. It has the same type of load-store architecture as the XAP4 and XAP5, but has 32-bit registers and 32-bit buses for Data and Address.