History of XAP processor in Timeline

By Popular Timelines Editorial Team · Updated: February 28, 2026

The XAP processor is a RISC architecture CPU, available in 16-bit and 32-bit variants, designed by Cambridge Consultants. It is tailored for mixed-signal integrated circuits, making it suitable for sensor and wireless applications like Bluetooth, Zigbee, GPS, RFID, and NFC. XAP processors are commonly used in battery-powered, low-energy, high-volume products, wireless sensor networks, and medical devices where energy efficiency is paramount.

1994: XAP1 Processor Design

In 1994, the XAP1 was designed for wireless and sensor ASIC projects at Cambridge Consultants. It was a small, 3,000-gate, Harvard architecture, 16-bit processor with a 16-bit data bus and an 18-bit instruction bus designed for programs stored in on-chip ROM.

1999: Launch of XAP2 Microprocessor

In 1999, the XAP2, a more advanced microprocessor, was developed and launched. It featured a Harvard architecture and utilized 16-bit data paths, with a more conventional 16-bit instruction width, enhancing compatibility with program storage solutions and included a C compiler and the XAPASM assembler for its assembly language.

2003: XAP3 Processor Design

In 2003, the XAP3 was an experimental 32-bit processor designed at Cambridge Consultants. It was optimized for low cost, low energy ASIC implementations using modern CMOS semiconductor process technologies and used a Von Neumann architecture.

2005: XAP4 Processor Design

In 2005, the XAP4, a new 16-bit processor, was designed to supersede the XAP2, taking into account the experience gained on XAP3 and the evolving requirements of ASIC designs. XAP4 is a very small, 12,000-gate, Von Neumann bus, 16-bit processor core capable of addressing a total of 64 Kbytes of memory for programs, data and peripherals.

2006: Development of XAP5 Commenced

In 2006, development of an extended version of the XAP architecture commenced, leading to the XAP5.

July 2008: XAP5 Announced

In July 2008, the XAP5 was announced. It is a 16-bit processor with a 24-bit address bus, making it capable of running programs from memory up to 16 MB.

2013: XAP6 Processor Launch

In 2013, the XAP6, a 32-bit processor, was launched. It has the same type of load-store architecture as the XAP4 and XAP5, but has 32-bit registers and 32-bit buses for Data and Address.